Principal Engineer Architect

☞ Microchip Technology Inc.

Visualizza: 242

Giorno di aggiornamento: 24-10-2024

Località: Heilbronn Baden-Württemberg

Categoria: Alta tecnologia Meccanico / Tecnico Elettrico / Elettronico

Industria: Electrical Electronic Manufacturing Semiconductors

Posizione: Mid-Senior level

Tipo di lavoro: Full-time

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Contenuto del lavoro

Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip’s fast-growing Analog Power and Interface Division (APID) is looking for an experienced and motivated Principle Design For Test (DFT) engineer to participate in a talented test architecture team to define and implement best DFT practices to help make designs more easily testable, more cost effective and provide reusable building blocks that can be used for multiple semiconductor device test applications. This individual should be self-driven, motivated, and capable of embracing a fast paced, continuously evolving, and improving culture. Experience in all stages of new product test development, DFT methodologies and proven design and test skills are critical to this position. The candidate should have excellent communication skills which are required to span across global teams and shared test applications within Microchip.

Responsibilities
  • Perform detailed review of design objective specifications (DOS) and evaluate/define design for testability (DFT) features required
  • Utilize experience in DFT implementation for analog and mixed-signal testing parameters
  • Provide technical leadership of DFT architectures
  • Accompany design projects starting from DOS phase 0.3 (early project definition phase) until RTP (release to production)
  • Working in close collaboration with various product line teams including design, test, applications, and product engineering, etc.
  • Define DFT requirements and write detailed DFT manual to be used by design and test team members
  • Match parameters from Electrical Characteristics table in DOS with critical ATE testing parameters and methods
  • Apply knowledge of ATE tester instruments and measurement specifications
  • Employ knowledge of ATE load board restrictions including layout and key testing requirements & accuracies
  • Cooperate with worldwide cross-functional teams (marketing, application, design, layout, lab, and test engineers)
Job Requirements
  • A university degree in Electrical or Computer Engineering with 10+ years experience developing ATE analog/mixed-signal test solutions including DFT applications
  • Analog design experience/exposure required for close development of DFT IP blocks, ability to read schematics and understand circuit needs and tradeoffs
  • Experience with analog and mixed-signal ATE platforms (ex: Eagle, Teradyne, SPEA, LTX)
  • Must possess an in-depth knowledge of analog, power and mixed-signal device theory and test methodology
  • Understand block diagrams of analog blocks like buck/boost regulators, linear regulators, PMIC’s, ADC’s, USB, and motor power delivery circuits
  • Understand device behavior and modes in terms of observability and controllability using different test conditions and possible impact on ATE tests
  • Have experience with Cadence Virtuoso or similar tool and ability to read design circuit schematics
  • Strong analytical, and problem-solving skills with an understanding of semiconductor test and FA methods
  • Must possess excellent communication skills and ability to work in a global multi-functional team environment
  • Strong team player and open minded
Highly Desired Skills
  • Experience on analog and mixed-signal ATE platforms: SPEA C600/DOT800, LTX Fusion EX, ETS-300/88/364
  • Understanding of DFT, BIST, SCAN, statistical process control, calibration theory, and test limit guard banding methodology
  • Generation of detailed Test Specifications from Device Specifications
  • Conducting comprehensive Test Plan Reviews and Peer Reviews
  • Experience with analog, power and mixed signal PCB design and layout (ex: Altium Designer)
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Scadenza: 08-12-2024

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