Type d’emploi: Vollzeit, Teilzeit, Festanstellung

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le contenu du travail

We are offering a position in the area of advanced timing sign-off validation methodology. Your task is the implementation of rules and methods for Static Timing Analysis (STA) to be applied as Sign-Off criterion and during chip synthesis. Therefore, you will be providing and verifying methodologies for the STA sign-off across a variety of state-of-the-art processes, but also for the latest ones. Another part of your tasks will be the improvement and optimization of the Signoff generation and verification processes. The Technical Ladder is a special career path for those who share innovative ideas, demonstrate comprehensive technical knowledge, show thought leadership, possess problem solving abilities and are able to create business value.
In your new role you will:
  • Be already an expert on timing signoff methodologies, understand specific requirements and fulfill them together with our team
  • Drive the timing signoff development process: starting from collection of requirements through data definition to a delivery
  • Ensure robust designs to cover performance and lifetime requirements
  • Correlate timing sign-off data to existing hardware
  • Work on concept improvements to enable better products
  • Cooperate closely with other expert groups to provide well-suited solutions and superior support our internal customers

You keep the customer informed appropriately, transparently, and regularly as well as you cooperate across boundaries and appreciate the contributions of other people. In your daily work you pursue high quality. Furthermore, you are a very motivated individual striving for in-depth understanding of technical details and able to translate ideas into improvement of provisioning processes.

You are best equipped for this task if you have:
  • A technical degree in Electrical Engineering, Computer Science, Physics or a similar qualification
  • At least 5 years experience in timing analysis and verification and/or in digital chip design
  • Founded experience in Static Timing Analysis and SPICE simulation
  • Advanced programming skills in Perl/ Python and SQL
  • A good level of understanding hardware description languages as well as circuit design
  • Background knowledge of uncertainties in chip design and timing verification desirable
  • Fluent communication skills in English and use them to share your knowledge actively; German is a plus

In our headquarters in Neubiberg near Munich, more than 6000 employees are working in research & development, several central functions, IT and many more.


Part of your life. Part of tomorrow.

Infineon is a world leader in semiconductor solutions that make life easier, safer, and greener. Our solutions for efficient energy management, smart mobility, and secure, seamless communications link the real and the digital world.

* The term gender in the sense of the General Equal Treatment Act (GETA) or other national legislation refers to the biological assignment to a gender group. At Infineon we are proud to embrace (gender) diversity, including female, male and diverse.
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Date limite: 01-12-2024

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