Master Thesis - Design and Implementation of an Ultra-Low Power, High-Sensitivity Dynamic Comparator for Qubit Readout

☞ Forschungszentrum Jülich

Ver: 153

Día de actualización: 07-10-2024

Ubicación: Jülich North Rhine-Westphalia

Categoría: Educación / Entrenamiento Pasantía / Nivel de entrada

Industria: Research

Posición: Internship

Tipo de empleo: Full-time

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Contenido de trabajo

Your JobQuantum computing is one of the most promising candidates today for significantly enhancing classical computing is one of the most promising candidates today for significantly enhancing classical computing. This requires thousands of quantum bits (qubits), leading to the need of scalable electronics to interface them. The major challenge in developing electronics to interface semiconduvtor qubits si the typical operating temperature of well below 1 Kelvin and the requirement for ultra-low power dissipation. Our group is actively researching on developing integrated circuits for this environment in commercial FDSOI-CMOS nodes.You will have the chance to work together with us on this major challenge by developing an ultra-low power comparator to readout the state of a qubit. To reach the required precision, you will implement a novel digital calibration loop for the comparator and benchmark it to existing analog calibration concepts.The specific tasks are to design, layout and verify an ultra-low power, low noise comparator with a digital calibration loop:
  • Analog Design and simulation of a dynamic comparator and a DAC
  • Digital design and simulation of a calibration logic
  • Mixed-Mode Simulation to evaluate the overall performance of the design
  • Layout and aprasitic extractions of the analog calibration loop
  • Comparison to existing comparators with analog calibration
Your Profile
  • Enrolled in an M. Sc. course at a European university for Electrical Engineering, Physics or similar fields
  • Experience with analog circuit design and the Cadence analog design enviroment as well as SPICE simulations
  • First experience with in full custom layout for state of the art technologies is a plus
  • Knowledge of digital circuit description (Verilog or VHDL)
  • Good English capabilities and optionally knowledge of German
Please apply for the position even if you do not have every required skills and knowledge but are curious to learn more.Our OfferWe work on the very latest issues that impact our society and are offering you the chance to actively help in shaping the change! We support you in your work with:
  • Opportunity to work on highly-relevant engineering challenges with state of the art technologies
  • Continuous scientific mentoring by your scientific advisor as well as a close integration in the international research group
  • Being involved in various steps of the development flow for an integrated circuit
  • Excellent scientific and technical infrastructure
  • Flexible work hours and the possibility to partially work from home
In addition to exciting tasks and a collaborative working atmosphere at Jülich, we have a lot more to offer: https://go.fzj.de/benefitsWe welcome applications from people with diverse backgrounds, e. g. in term of age, gender, disability, sexual orientation / identity, and social, ethnic and religious origin. A diverse and inclusive working environment with equal opportunities in which everyone can realize their potential is important to us.
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Plazo: 21-11-2024

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